Effect of fission products on tensile strength of UO<sub>2</sub> Σ3 (111)/[1<math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si1.svg" class="math"><mover accent="true"><mn>1</mn><mo stretchy="true">¯</mo></mover></math>0] and UO<sub>2</sub> Σ11 (1<math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si1.svg" class="math"><mover accent="true"><mn>1</mn><mo stretchy="true">¯</mo></mover></math>3)/[110] grain boundaries from first-principles study

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Intel® Software Guard Extensions (Intel® SGX) — Intel Developer Documentation

require some technical skills and some features may require a paid

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Besides the Test PLA, the 386 has another PLA called the Entry PLA that maps opcodes to microcode entry points. One of its input bits is a "protected mode" flag. Many instructions have both a real-mode and a protected-mode entry point -- for instance, MOV ES, reg maps to address 009 (a single microcode line) in real mode, but to 580 (which initiates a full descriptor load with protection tests) in protected mode. The trick that makes V86 work is to define this flag as: